1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a nonvolatile memory device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for reducing a cell size.
2. Discussion of the Related Art
Nonvolatile memory devices, such as flash EEPROMs and flash memory cards, are one of the most active areas in research and development throughout the semiconductor industry.
Generally, in using nonvolatile semiconductor memory devices, such as EEPROM and flash EEPROM, as mass storage media, one of the serious drawbacks is a high cost-per-bit of the memories. Furthermore, when the nonvolatile memories are applied to portable products, low power consumption is required to be used in nonvolatile memory chips. Thus, a multibit-per-cell has been studied to lower the cost-per-bit in the nonvolatile memory device.
The data density of a conventional nonvolatile memory lies in a one to one fashion to the number of memory cells. However, since a multibit cell stores two-bit data or more in one memory cell, it enhances the density of data on the same chip area without increasing size of the memory cell.
In order to implement the multibit cell, more than three threshold voltage levels should be programmed on each memory cell. For instance, in order to store two-bit data in every cell, the respective cells must be programmed with four (2.sup.2 =4) threshold levels. The four threshold levels correspond to logic states 00, 01, 10, and 11, respectively.
In the multi-level program, the most critical problem is that the respective threshold voltage levels have a statistical distribution. A typical distribution value is about 0.5V.
When the distribution is reduced by precisely adjusting the respective threshold levels, more levels can be programmed so that the number of bits per cell is increased. A method of programming using repeated programming and verification is generally used to reduce the voltage distribution.
According to this method, a series of voltage pulses are applied to the cells in order to program the nonvolatile memory cell at intended threshold levels. To verify whether a cell reaches an intended threshold level, a reading operation is performed between the respective programming voltage pulses.
During verification, when the verified threshold level reaches the intended threshold level, programming stops. However, the method of repeated programming and verification is not able to reduce the error distribution of the threshold level due to the limited pulse width of a programmed voltage. In addition, since the algorithm of repeated programming and verification is implemented with an additional circuit, the area of peripheral circuits of the chip is increased. Furthermore, the repetitive method prolongs the programming time. In order to solve such a drawback, R. Cernea of SunDisk Co., Ltd. suggested a method of simultaneous programming and verification in U.S. Pat. No. 5,422,842 issued on Jun., 6, 1996.
FIG. 1A illustrates a symbol and circuit diagram of a nonvolatile memory, proposed by Cernea. As shown in FIG. 1A, the nonvolatile memory cell includes a control gate 1, a floating gate 2, a source 3, a channel area 4, and a drain 5.
When voltages sufficient to cause programming are applied to the control gate 1 and the drain 5, a current flows between the drain 5 and the source 3. The current is compared to a reference current. When the current reaches a value equal to or smaller than the reference current, a programming completion signal is produced.
The above-mentioned procedure is illustrated in FIG. 1B. An auto-verification of a programmed condition with same time programming can compensate for the disadvantage of the repetition of the program verification to some extent. However, R. Cernea suggests using neither a separate program gate for programming operation nor a structure having separated paths for programming and sensing (or verifying) current. Moreover, the threshold level cannot be adjusted by a voltage applied to the control gate of the memory cell. Therefore, separate optimization of the operations for programming and sensing is not feasible. Since the programming current and the monitoring current are not separated from each other, it is hard to directly control the threshold voltage of cell.
On the other hand, U.S. Pat. No. 5,043,940, issued on Aug. 27, 1991, discloses a method of executing a multi-level programming where voltages applied to each terminal of the memory cell are fixed while reference currents for respective levels are varied. However, even in this method, as shown in FIG. 1B, the relation between the reference currents for detection and the cell threshold voltages is neither explicit nor linear.
Therefore, the aforementioned prior art such as a current controlled type programming method still has a disadvantage in that a direct and effective multi-level control is not easy.
In order to eliminate these problems, a programming method of a voltage control type controlling the threshold voltage of a cell by means of a voltage applied to the control gate of the cell has been disclosed in copending U.S. patent application Ser. No. 08/542,651, filed Oct. 13, 1995, which is hereby incorporated by reference. According to this method, a shift of the threshold voltage of a cell is identical to a shift of the control gate voltage. Therefore, the threshold voltage is adjusted precisely.
Cell structures of EEPROM and flash EEPROM can be classified into two kinds depending upon the position of a floating gate on a channel region.
One is a simple stacked gate structure in which the floating gate fully covers the channel region and the other is a split-channel structure in which the floating gate covers only a portion of the channel region between source and drain. The channel region without the floating gate is called a select transistor. The select transistor and the floating gate transistor are included in a memory cell and connected in series with each other.
The split-channel type cell is also classified into two types depending upon methods of forming the select transistor; a merged-split-gate and a split-gate-cell.
In the merged-split-gate cell, a control gate electrode of the floating gate transistor and a gate electrode of the select transistor are integrated into one, whereas the control gate electrode of the floating gate transistor and the gate electrode of the select transistor are separated from each other in the split-gate-cell. The select transistor has been introduced to prevent a problem of over-erasure and to make the formation of contactless virtual ground array easily. Besides, the split-gate-cell makes a hot electron injection from a source side easier.
FIG. 2A illustrates a diagram of a conventional nonvolatile memory cell of the simple stacked gate type, and FIG. 2B illustrates a diagram of a conventional nonvolatile memory cell of the split channel type. FIGS. 2A and 2B illustrate structures of conventional nonvolatile memory cells together with erasure and programming processes. As shown in FIG. 2A, the simple stacked gate type memory cell includes a control gate 6, a floating gate 7, a source 8, a drain 9, and a channel region 10. As shown in FIG. 2B, the split channel type memory cell includes a control gate 13, a floating gate 14, a source 15, a drain 16, a channel region 17, and a gate 18 for erasure.
Referring to FIG. 2B, since the erasure gate 18 is not needed during the programming operation, each of the conventional cells shown in FIGS. 2A and 2B actually becomes a structure the same as a double polygate structure.
In summary, in considering all of the prior art up to now, since a programming has been executed only with electrodes of the control gate, the source and/or the drain, it is difficult to separate paths for programming and verifying (or sensing) current within a memory cell. Therefore, a direct and effective multi-level control is difficult in memory cell.
While the merged-split-gate cell employs a drain side hot electron injection mechanism as a programming method, the split-gate cell employs a source side hot electron injection mechanism as a programming method. Like other EEPROMs, FN (Folwer-Nordheim) tunneling is employed for erasure.
The split-channel cells, using hot electron injection mechanism, need more power consumption in programming than in tunneling. In hot carrier injection, the merged-split-gate cell cannot easily execute two different kinds of ion injection into the drain region, whereas there are problems in optimizing an oxide film thickness between the select transistor and the floating gate transistor as well as preventing degradation of the read current caused by degradation of the oxide film in the split gate cell.
In the conventional split-channel cell, the electron injection(programming and data writing) has been carried out by hot carrier injection through a gate oxide film adjacent to the channel, and the electron erasure(deletion of data) has been carried out through a third gate, a control gate, or a gate oxide film adjacent to a channel.
Since the nonvolatile memory device disclosed in the previously mentioned application Ser. No. 08/542,651 employs a program gate as well as a gate oxide film for erasure, the gate oxide film must be formed with a thickness of 10 nm or below and requires an additional process for forming the high purity gate oxide film. In addition, ONO (Oxide/Nitride/Oxide) structure is required between the floating gate and the control gate so as not to reduce coupling due to such an erasure method. Thus, by employing the program gate for erasure, writing operations in the polyoxide film is improved.